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Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
The S-8253A/B Series are protection ICs for 2-serial or 3-serial cell lithium-ion rechargeable batteries and include high-accuracy voltage detectors and delay circuits. These ICs are suitable for protecting lithium-ion battery packs from overcharge, overdischarge and overcurrent.
Features
(1) High-accuracy voltage detection for each cell * * Overcharge detection voltage n (n = 1 to 3) 3.9 V to 4.4 V (50 mV steps) Accuracy 25 mV *1 Accuracy 50 mV Overcharge release voltage n (n = 1 to 3) 3.8 V to 4.4 V *1. Overcharge release voltage = Overcharge detection voltage - Overcharge hysteresis voltage (Overcharge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV steps.) * * Overdischarge detection voltage n (n = 1 to 3) 2.0 V to 3.0 V (100 mV steps)
*2
Accuracy 80 mV
Overdischarge release voltage n (n = 1 to 3) 2.0 V to 3.4 V Accuracy 100 mV *2. Overdischarge release voltage = Overdischarge release voltage - Overdischarge hysteresis voltage (Overdischarge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.2 V to 0.7 V in 100 mV steps.)
(2)
Three-level overcurrent detection (including load short circuiting detection) * Overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV steps) Accuracy 25 mV * Overcurrent detection voltage 2 0.5 V (fixed) * Overcurrent detection voltage 3 1.2 V (fixed) Delay times (overcharge, overdischarge, overcurrent) are generated by an internal circuit (external capacitors are unnecessary). Charge/discharge operation can be inhibited via the control pin. 0 V battery charge function available/unavailable are selectable. High-voltage withstand devices Wide operating voltage range Wide operating temperature range Low current consumption * * Operation mode Power-down mode 28 A max. (+25C) 0.1 A max. (+25C) Absolute maximum rating: 26 V 2 V to 24 V -40C to +85 C
(3) (4) (5) (6) (7) (8) (9)
Applications
* * Lithium-ion rechargeable battery packs Lithium polymer rechargeable battery packs
Package
* 8-Pin TSSOP (Package drawing code: FT008-D)
Seiko Instruments Inc.
1
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Block Diagram
(1) S-8253A Series
Rev.2.1_00
VDD DOP Oscillator, counter, controller
COP
- + + - + - + - + -
VC1
- + + -
95 k VMP 900 k
VC2
- + + -
CTLH 200 nA CTL CTLM
VSS
Figure 1 Block Diagram (S-8253A Series)
2
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
(2) S-8253B Series
VDD DOP Oscillator, counter, controller
COP
- + + - + - + - + -
VC1
- + + -
95 k VMP 900 k
VC2
- + + -
CTLH 200 nA CTL CTLM
VSS
Figure 2 Block Diagram (S-8253B Series)
Seiko Instruments Inc.
3
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Product Code Structure
1. Product Name S-8253 - x xx - T8T1
Rev.2.1_00
Indicates package type and packing specification of IC
T8T1 : 8-Pin TSSOP
*1
Additional number Sequentially set from AA to ZZ Product series A: 2-cell B: 3-cell *1. Refer to the taping drawing. 2. Product Name List Table 1 S-8253A Series (for 2-Serial Cell)
Overcharge Overdischarge Overdischarge Overcharge Product Detection Voltage Release Voltage Detection Voltage Release Voltage Name/Parameter VCL VDL VDU VCU S-8253AAA-T8T1 4.35 0.025 V 4.05 0.050 V 2.40 0.080 V 2.70 0.100 V Overcurrent Detection Voltage 1 VIOV1 0.30 0.025 V 0 V Battery Charge
Available
Remark If a product with the required detection voltage does not appear in the above list, contact our sales office. Table 2 S-8253B Series (for 3-Serial Cell)
Overcharge Overdischarge Overdischarge Overcharge Product Detection Voltage Release Voltage Detection Voltage Release Voltage Name/Parameter VCL VDL VDU VCU S-8253BAA-T8T1 4.35 0.025 V 4.05 0.050 V 2.40 0.080 V 2.70 0.100 V Overcurrent Detection Voltage 1 VIOV1 0.30 0.025 V 0 V Battery Charge
Available
Remark If a product with the required detection voltage does not appear in the above list, contact our sales office.
4
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Pin Assignment
8-Pin TSSOP Top view
DOP COP VMP CTL 1 2 3 4 8 7 6 5 VDD VC1 VC2 VSS
Table 3 S-8253A Series Pin No. 1 2 3 Pin Name DOP COP VMP Function Connection of discharge control FET gate (CMOS output) Connection of charge control FET gate (Nch open-drain output) Voltage detection between VDD and VMP (overcurrent detection pin) Input of charge/discharge control signal, pin for shortening test time (L: Normal operation, H: Charge/discharge inhibited, M (VDD x 1/2): Test time reduced) Negative power supply input, negative voltage connection for battery 2 *1 No connection Connection for negative voltage of battery 1 and positive voltage of battery 2 Connection for positive power supply input and positive voltage of battery 1
Figure 3 4 CTL
5 6 7 8
VSS VC2 VC1 VDD
*1. No connection is electrically open. This pin can be connected to VDD or VSS. Remark For the external views, refer to package drawings. Table 4 S-8253B Series Pin No. 1 2 3 Pin Name DOP COP VMP Function Connection of discharge control FET gate (CMOS output) Connection of charge control FET gate (Nch open-drain output) Voltage detection between VDD and VMP (overcurrent detection pin) Input of charge/discharge control signal, pin for shortening test time (L: Normal operation, H: Charge/discharge inhibited, M (VDD x 1/2): Test time reduced) Connection for negative power supply input and negative voltage of battery 3 Connection for negative voltage of battery 2 and positive voltage of battery 3 Connection for negative voltage of battery 1 and positive voltage of battery 2 Connection for positive power supply input and positive voltage of battery 1
4
CTL
5 6 7 8
VSS VC2 VC1 VDD
Remark For the external views, refer to package drawings.
Seiko Instruments Inc.
5
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Absolute Maximum Ratings
Table 5 Parameter Input voltage between VDD and VSS Input pin voltage VMP pin input voltage DOP pin output voltage COP pin output voltage CTL input pin voltage Power dissipation Operating temperature range Storage temperature range Symbol VDS VIN VVMP VDOP VCOP VIN_CTL PD Topr Tstg Applicable Pins VC1, VC2 VMP DOP COP CTL
Rev.2.1_00
(Ta = 25C unless otherwise specified)
Rating
Unit V
VSS - 0.3 to VSS + 26
VSS - 0.3 to VDD+ 0.3 VSS - 0.3 to VSS + 26 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VVMP + 0.3 VSS - 0.3 to VDD+ 0.3 300 mW -40 to +85 -40 to +125 C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.
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Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Electrical Characteristics
Table 6
Parameter DETECTION VOLTAGE Overcharge detection voltage n Overcharge release voltage n Overdischarge detection voltage n Overdischarge release voltage n Overcurrent detection voltage 1 Overcurrent detection voltage 2 Overcurrent detection voltage 3 Temperature coefficient 1 Temperature coefficient 2 DELAY TIME Overcharge detection delay time Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 0 V BATTERY CHARGE FUNCTION 0 V charge starting charger voltage 0 V battery charge inhibition battery voltage INTERNAL RESISTANCE Resistance between VMP and VDD Resistance between VMP and VSS INPUT VOLTAGE Operating voltage between VDD and VSS CTL input voltage, high CTL input voltage, low INPUT CURRENT Current consumption during operation Current consumption at power down VC1 pin current VC2 pin current CTL pin current, high CTL pin current, low OUTPUT CURRENT COP pin leakage current COP pin sink current DOP pin source current DOP pin sink current Symbol VCUn VCLn VDLn VDUn VIOV1 VIOV2 VIOV3 TCOE1 TCOE2 tCU tDL tIOV1 tIOV2 tIOV3 Conditions Min.
(Ta = 25C unless otherwise specified)
Typ. Max. Unit Test
Conditions
Test Circuit 1 1 1 1 1 1 1 - - 1 1 1 1 1
VCUn V 3.90 to 4.40 V, adjustable VCUn - 0.025 VCUn + 0.025 3.80 to 4.40 VCL VCU VCLn - 0.05 VCLn VCLn + 0.05 V V, VCLn VCLn + 0.025 VCL = VCU VCLn - 0.025 adjustable VDLn V 2.0 to 3.0 V, adjustable VDLn - 0.080 VDLn + 0.080 VDUn 2.0 to 3.40 V, VDL VDU VDUn - 0.10 VDUn + 0.10 V adjustable VDUn VDL = VDU VDUn - 0.08 VDUn + 0.08 VIOV1 - VIOV1 + 0.05 to 0.3 V, adjustable VIOV1 V 0.025 0.025 V VDD - 0.60 VDD - 0.50 VDD - 0.40 V VDD - 1.2 VDD - 0.9 VDD - 1.5 *1 0 1.0 -1.0 mv/C Ta = 0 to 50C *2 0 0.5 -0.5 mv/C Ta = 0 to 50C FET gate capacitance = 2000 pF 0 V charge available 0 V charge un available V1 = V2 = V3 = 3.5 V VVMP = VSS V1 = V2 = V3 = 1.8 V VVMP = VDD Output voltage of DOP and COP fixed V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 1.5 V V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 3.5 V VCTL1 = VDD V1 = V2 = V3 = 3.5 V VCTL1 = VSS VCOP = 24 V VCOP = VSS + 0.5 V VDOP = VDD - 0.5 V VDOP = VSS + 0.5 V 0.92 115 7.2 3.6 150 1.15 144 9 4.5 320 1.38 173 10.8 5.4 540 s ms ms ms s
1 1 1 1 2 2 2 - - 3 3 4 4 4
V0CHA V0INH
0.4
0.8 0.7
1.5 1.1
V V
12 12
5 5
RVMD RVMS
70 450
95 900
120 1800
k k
6 6
2 2
VDSOP VCTLH VCTLL IOPE IPDN IVC1 IVC2 ICTLH ICTLL ICOH ICOL IDOH IDOL
2 VDD - 0.5 -0.3 -0.3 -0.4 10 10 10
14 0 0 -0.2
24 VSS + 0.5 28 0.1 0.3 0.3 0.1 0.1
V V V A A A A A A A A A A
- 7 7 5 5 9 9 8 8 10 10 11 11
- 1 1 2 2 3 3 3 3 4 4 4 4
*1. Voltage temperature coefficient 1: Overcharge detection voltage *2. Voltage temperature coefficient 2: Overcurrent detection voltage 1
Seiko Instruments Inc.
7
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Test Circuits
1.
Rev.2.1_00
Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, overdischarge release voltage (Test condition 1, test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are low (VDD x 0.1 V or lower) (this status is referred to as the initial status). * Overcharge detection voltage 1 (VCU1), overcharge release voltage 1 (VCL1) Overcharge detection voltage 1 (VCU1) is the voltage of V1 when the voltage of the COP pin is high (VDD x 0.9 V or more) after the V1 voltage has been gradually increased starting at the initial status. Overcharge release voltage 1 (VCL1) is the voltage of V1 when the voltage at the COP pin is low after the V1 voltage has been gradually decreased. * Overdischarge detection voltage 1 (VDL1), overdischarge release voltage 1 (VDU1) Overdischarge detection voltage 1 (VDL1) is the voltage of V1 when the voltage of the DOP pin is high after the V1 voltage has been gradually decreased starting at the initial status. Overdischarge release voltage 1 (VDU1) is the voltage of V1 when the voltage at the DOP pin is low after the V1 voltage has been gradually increased. By changing Vn (n = 2: S-8253A Series, n = 2, 3: S-8253B Series) the overcharge detection voltage (VCUn), overcharge release voltage (VCLn), overdischarge detection voltage (VDLn), and overdischarge release voltage (VDUn) can be measured in the same way as when n = 1.
2.
Overcurrent detection voltage (Test condition 2, test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are low (this status is referred to as the initial status). * Overcurrent detection voltage 1 (VIOV1) Overcurrent detection voltage 1 (VIOV1) is the voltage of V5 when the voltages of the COP and DOP pins are high after the V5 voltage has been gradually increased starting at the initial status. * Overcurrent detection voltage 2 (VIOV2) Overcurrent detection voltage 2 (VIOV2) is the voltage of V5 when the voltages of the COP and DOP pins are high within the minimum and maximum values of overcurrent detection time 2 (tIOV2) after the voltage of V5 was instantaneously increased (within 10 s) starting at the initial status. * Overcurrent detection voltage 3 (VIOV3) Overcurrent detection voltage 3 (VIOV3) is the voltage of V5 when the voltages of the COP and DOP pins are high within the minimum and maximum values of overcurrent detection time 3 (tIOV3) after the voltage of V5 was instantaneously increased (within 10 s) starting at the initial status.
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Seiko Instruments Inc.
Rev.2.1_00
3.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Overcharge detection delay time, overdischarge detection delay time (Test condition 3, test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are low (this status is referred to as the initial status). * Overcharge detection delay time (tCU) The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from low to high after the voltage of V1 is instantaneously changed from overcharge detection voltage 1 (VCU1) - 0.2 V to overcharge detection voltage 1 (VCU1) + 0.2 V (within 10 s) starting at the initial status. * Overdischarge detection delay time (tDL) The overdischarge detection delay time (tDL) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V1 is instantaneously changed from overdischarge detection voltage 1 (VDL1) + 0.2 V to overdischarge detection voltage 1 (VDL1) - 0.2 V (within 10 s) starting at the initial status.
4.
Overcurrent detection delay time (Test condition 4, test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are low (this status is referred to as the initial status). * Overcurrent detection delay time 1 (tIOV1) Overcurrent detection delay time 1 (tIOV1) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 0.35 V (within 10 s) starting at the initial status. * Overcurrent detection delay time 2 (tIOV2) Overcurrent detection delay time 2 (tIOV2) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 0.7 V (within 10 s) starting at the initial status. * Overcurrent detection delay time 3 (tIOV3) Overcurrent detection delay time 3 (tIOV3) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 1.6 V (within 10 s) starting at the initial status.
5.
Power consumption during operation, power consumption at power-down (Test condition 5, test circuit 2)
* Power consumption during operation (IOPE), power consumption at power-down (IPDN) The power consumption during operation (IOPE) is the current of the VSS pin (ISS) when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF. The power consumption at power-down (IPDN) is the current of the VSS pin (ISS) when V1 = V2 = 1.5 V (S-8253A Series), V1 = V2 = V3 = 1.5 V (S-8253B Series), S1 = OFF, and S2 = ON.
Seiko Instruments Inc.
9
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
6. Resistance between VMP and VDD, resistance between VMP and VSS (Test condition 6, test circuit 2)
Rev.2.1_00
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF (this status is referred to as the initial status). * Resistance between VMP and VDD (RVMD) The resistance between VMP and VDD (RVMD) is determined based on the current of the VMP pin (IVMD) after S1 and S2 are switched to OFF and ON, respectively, starting at the initial status. S-8253A Series: RVMD = (V1 + V2)/IVMD S-8253B Series: RVMD = (V1 + V2 + V3)/IVMD * Resistance between VMP and VSS (RVMS) The resistance between VMP and VSS (RVMS) is determined based on the current of the VMP pin (IVMS) after V1 = V2 = 1.8 V (S-8253A Series) or V1 = V2 = V3 = 1.8 V (S-8253B Series) are set starting at the initial status. S-8253A Series: RVMS = (V1 + V2)/IVMS S-8253B Series: RVMS = (V1 + V2 + V3)/IVMS
7.
CTL pin input voltage (Test condition 7, test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are low (this status is referred to as the initial status). * CTL pin input voltage (high) (VCTLH) The CTL pin input voltage (high) (VCTLH) is the voltage of V4 when the voltages of the COP and DOP pins are high after the voltage of V4 has been gradually increased starting at the initial status. Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0.35 V, and the COP and DOP pins are high (this status is referred to as the initial status). * CTL pin input voltage (low) (VCTLL) The CTL pin input voltage (low) (VCTLL) is the voltage of V4 when the voltages of the COP and DOP pins are low after the voltage of V4 has been gradually decreased starting at the initial status.
8.
CTL pin current (Test condition 8, test circuit 3)
* CTL current (high) (ICTLH), CTL pin current (low) (ICTLL) The CTL pin current (high) (ICTLH) is the current that flows through the CTL pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = ON, S4 = OFF. The CTL current (low) (ICTLL) is the current that flows through the CTL pin when S3 = OFF and S4 = ON after that.
10
Seiko Instruments Inc.
Rev.2.1_00
9.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
VC1 pin current, VC2 pin current (Test condition 9, test circuit 3)
* VC1 pin current (IVC1), VC2 pin current (IVC2) The VC1 pin current (IVC1) is the current that flows through the VC1 pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = OFF, S4 = ON. Similarly, the VC2 pin current (IVC2) is the current that flows through the VC2 pin under these conditions (S-8253B Series only).
10. COP pin leakage current, COP pin sink current (Test condition 10, test circuit 4)
* COP pin leakage current (ICOH), COP pin sink current (ICOL) The COP pin leakage current (ICOH) is the current that flows through the COP pin when V1 = V2 = 12 V (S-8253A Series), V1 = V2 = V3 = 8 V (S-8253B Series), S6 = S7 = S8 = OFF, and S5 = ON. The COP pin sink current (ICOL) is the current that flows through the COP pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V6 = 0.5 V, S5 = S7 = S8 = OFF, and S6 = ON.
11. DOP pin source current, DOP pin sink current (Test condition 11, test circuit 4)
* DOP pin source current (IDOH), DOP pin sink current (IDOL) The DOP pin source current (IDOH) is the current that flows through the DOP pin when V1 = V2 = 1.8 V (S-8253A Series), V1 = V2 = V3 = 1.8 V (S-8253B Series), V7 = 0.5 V, S5 = S6 = S8 = OFF, and S7 = ON. The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V8 = 0.5 V, S5 = S6 = S7 = OFF, and S8 = ON.
12. 0 V charge start battery charger voltage or 0 V charge inhibition battery voltage (Test condition 12, test circuit 5)
* 0 V charge start battery charger voltage (V0CHA): Products that available 0 V charge The COP pin voltage should be lower than V0CHA max. -1 V when V1 = V2 = 0 V (S-8253A Series), V1 = V2 = V3 = 0 V (S-8253B Series), and V9 = VVMP = V0CHA max.. * 0 V charge inhibition battery voltage (V0INH): Products that unavailable 0 V charge The COP pin voltage should be higher than VVMP - 1 V when V1 = V2 = V0INH min. (S-8253A Series), V1 = V2 = V3 = V0INH min. (S-8253B Series), and V9 = VVMP = 24 V.
Seiko Instruments Inc.
11
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Rev.2.1_00
S-8253A V V 1 DOP 1 M 2 COP V5 3 VMP VC2 6 1 F 4 CTL V4 VSS 5 V4 4 CTL VC1 7 V2 V5 3 VMP VDD 8 V1 1 M 2 COP V V 1 DOP
S-8253B VDD 8 V1 VC1 7 V2 VC2 6 1 F VSS 5 V3
Test Circuit 1
S-8253A 1 DOP S1 2 COP VC1 7 V2 A 3 VMP VC2 6 1 F S2 4 CTL VSS 5 A S2 4 CTL A 3 VMP VDD 8 V1 S1 2 COP 1 DOP
S-8253B VDD 8 V1 VC1 7 V2 VC2 6 1 F VSS 5 A V3
Test Circuit 2
S-8253A 1 DOP S3 2 COP VC1 7 A V2 3 VMP VC2 6 1 F A S4 4 CTL VSS 5 S4 A 4 CTL 3 VMP VDD 8 V1 S3 2 COP 1 DOP
S-8253B VDD 8 V1 VC1 7 A V2 VC2 6 A 1 F VSS 5 V3
Test Circuit 3 Figure 4 Test Circuit (1/2)
12
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
S5
S7 V7 A V8 A 2 COP 1 DOP
S-8253A VDD 8 V1 VC1 7 V2
S5
S7 V7 A V8 A 2 COP 1 DOP
S-8253B VDD 8 V1 VC1 7 V2
V6
3 VMP
VC2 6 1 F
V6
3 VMP
VC2 6 1 F V3
S6
S8
4 CTL
VSS 5
S6
S8
4 CTL
VSS 5
Test Circuit 4
S-8253A 1 DOP VDD 8 V1 2 COP V 1 M 3 VMP V9 4 CTL VSS 5 VC2 6 1 F V9 4 CTL VSS 5 VC1 7 V2 V 1 M 3 VMP VC2 6 1 F V3 2 COP VC1 7 V2 1 DOP S-8253B VDD 8 V1
Test Circuit 5 Figure 4 Test Circuit (2/2)
Seiko Instruments Inc.
13
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Description of Operation
Remark Refer to " Standard Circuit ".
Rev.2.1_00
1. Normal status When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than the specified value (the VMP pin voltage is higher than VDD - VIOV1), the charging and discharging FETs are turned on. Caution When the battery is connected for the first time, discharging may not be enabled. In this case, short the VMP and VDD pins or connect the charger to restore the normal status. 2. Overcharge status When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP pin becomes high impedance. Because the COP pin is pulled up to the EB+ pin voltage by an external resistor, the charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is released when one of the following two conditions holds. a) All battery voltages become VCLn or lower. b) All of the battery voltages are VCUn or lower, and the VMP pin voltage is VDD - VIOV1 or lower (Since the discharge current flows through the body diode of the charging FET immediately after discharging is started when the charger is removed and a load is connected, the VMP pin voltage momentarily decreases by approximately 0.6 V from the VDD pin voltage. The IC detects this voltage and releases the overcharging status.) 3. Overdischarge status When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the overdischarging status. After discharging is stopped due to the overdischarge status, the S-8253A/B Series enters the power-down status. 4. Power-down status When discharging has stopped due to the overdischarge status, the VMP pin is pulled down to the VSS level by the RVSM resistor. When the VMP pin voltage is lower than VDD/2, the S-8253A/B Series enters the power-down status. In the power-down status, almost all the circuits of the S-8253A/B Series stop and the current consumption is IPDN or lower. The conditions of each output pin are as follows. a) COP Hi-Z b) DOP VDD The power-down status is released when the following condition holds. a) The VMP pin voltage is VDD/2 or higher. (A charger is connected.) The overdischarging status is released when the following condition holds. a) All of the battery voltages are VDLn or higher, and the VDD pin voltage is VDD/2 or higher. (A charger is connected.)
14
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
5. Overcurrent status The S-8253A/B Series has three overcurrent detection levels (VIOV1, VIOV2, and VIOV3) and three overcurrent detection delay times (tIOV1, tIOV2, and tIOV3) corresponding to each overcurrent detection level. When the discharging current becomes higher than the specified value (the difference of the voltages of the VMP and VDD pins is greater than VIOV1) and the state continues for tIOV1 or longer, the S-8253A/B Series enters the overcurrent status, in which the DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to the EB+ pin voltage to turn off the charging FET to stop charging, and the VMP pin is pulled up to the VDD voltage by the internal resistor RVMD. Operation of overcurrent detection levels 2, 3 (VIOV2, VIOV3) and overcurrent detection delay times 2, 3 (tIOV2, tIOV3) are the same as for VIOV1 and tIOV1. The overcurrent status is released when the following condition holds. a) The VMP pin voltage is VDD - VIOV1 or higher because a charger is connected or the load is released. Caution The impedance that enables automatic restoration varies depending on the battery voltage and set value of overcurrent detection voltage 1. 6. 0 V battery charge function Regarding the charging of a self-discharged battery (0 V battery), the S-8253A/B Series has two functions from which one should be selected. a) 0 V battery charging is allowed (0 V battery charging is available) When the charger voltage is higher than V0CHA, the 0 V battery can be charged. b) 0 V battery charging is prohibited (0 V battery charging is unavailable) When one of the battery voltages is lower than V0INH, the 0 V battery cannot be charged. Caution When the VDD pin voltage is lower than the minimum value of VDSOP, the operation of the S-8253A/B Series is not guaranteed.
Seiko Instruments Inc.
15
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Rev.2.1_00
7. Delay circuit The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter. (Example) Oscillator clock cycle (TCLK): Overcharge detection delay time (tCU): Overdischarge detection delay time (tDL): Overcurrent detection delay time 1 (tIOV1): Overcurrent detection delay time 2 (tIOV2):
280 s 1.15 s 144 ms 9 ms 4.5 ms
Caution The overcurrent detection delay time 2(tIOV2) and overcurrent detection delay time 3(tIOV3) start when the overcurrent detection voltage 1(VIOV1) is detected. As soon as the overcurrent detection voltage 2(VIOV2) or overcurrent detection voltage 3(VIOV3)is detected over the detection delay time for overcurrent 2(tIOV2) or overcurrent 3(tIOV3) after the detection of overcurrent 1, the S-8253A/B turns the discharging control FET off.
VDD DOP pin voltage VSS Overcurrent detection delay time 2 (tIOV2) VDD VIOV1 VIOV2 VSS Time 8. CTL pin The S-8253A/B Series has a control pin for charge/discharge control and reducing test time. The levels, "L", "H", and "M", of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation, charge/discharge inhibition, or test time reduction. The CTL pin takes precedence over the battery protection circuit. During normal use, short the CTL and VSS pins. Table 7 Conditions Set by CTL Pin
CTL Pin Potential Open High (VCTL VCTLH) Middle (VCTLL < VCTL < VCTLH) Low (VCTLL VCTL) Status of IC Charge/discharge inhibited status Charge/discharge inhibited status Delay time reduced status Normal status
*1
Time
VMP pin voltage
COP Pin Hi-Z Hi-Z (*2) (*2)
DOP Pin VDD VDD (*2) (*2)
*1. In the delay time reduced status, delay times are reduced in 1/60 to 1/30 scale. *2. The pin status is controlled by the voltage detection circuit. Caution1. 2. If the potential of the CTL pin is middle, overcurrent detection voltage 1 (VIOV1) does not operate. If you use the middle potential of the CTL pin, contact our sales office.
16
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Operation Timing Chart
1. Overcharge and overdischarge detection VHC VCUn VCLn Battery voltage VDUn VDLn VHD (n = 1 to 3) VDD DOP pin voltage VSS VEB+ COP pin voltage VSS VEB+ VDD VIOV1 VMP pin voltage Charger connection Load connection Mode
*1
Hi-Z
VSS
Overcharge detection delay time (tCU) <1> <2>
Overdischarge detection delay time (tDL) <1> <3> <1>
*1. <1>: Normal mode <2>: Overcharge mode <3>: Overdischarge mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 5
Seiko Instruments Inc.
17
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Rev.2.1_00
2. Overcurrent detection VCUn VCLn VDUn VDLn
(n = 1 to 3)
VHC
Battery voltage
VHD
VDD DOP pin voltage VSS VEB+ COP pin voltage VSS VDD VIOV1 VIOV2 VMP pin voltage VIOV3 V VSS Load connection
Overcurrent detection delay time 1 (tIOV1) Overcurrent detection delay time 2 (tIOV2) Overcurrent detection delay time 3 (tIOV3)
Hi-Z
Hi-Z
Hi-Z
Mode
*1
<1>
<2>
<1>
<2>
<1>
<2>
<1>
*1. <1>: Normal mode <2>: Overcurrent mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 6
18
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Standard Circuit
(1) S-8253A Series
Charging Discharging FET FET
EB+
RCOP RVMP
RDOP S-8253A 1 2 3 4 RCTL DOP COP VMP CTL VDD VC1 VC2 VSS 8 7 6 5 CVC1 CVSS RVC1 RVSS
CTL
EB- Figure 7 (2) S-8253B Series
Charging Discharging FET FET
EB+
RCOP RVMP
RDOP S-8253B 1 2 3 4 RCTL DOP COP VMP CTL VDD VC1 VC2 VSS 8 7 6 5 CVC1 CVC2 CVSS RVC1 RVC2 RVSS
CTL
EB- Figure 8
Seiko Instruments Inc.
19
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Table 8 Recommended Value for External Parts
No. 1 2 3 4 5 6 7 8 9 10 Symbol RVC1 RVC2 RDOP RCOP RVMP RCTL RVSS CVC1 CVC2 CVSS Recommended Value 1 1 5.1 1 5.1 0 0 0.1 0.1 1 Range 0 to 1 0 to 1 2 to 10 0.1 to 1 1 to 10 0 to 100 0 to 51 0 to 0.33 0 to 0.33 0 to 10 Unit k k k M k k F F F
Rev.2.1_00
Caution The standard circuit above does not guarantee proper operation. Evaluation in the actual application is needed to determine the correct constants.
Precautions
* * The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when a battery is connected. In this case, short the VMP and VDD pins or connect the battery charger to return to the normal mode. Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.
* *
20
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Characteristics (Typical Data)
(1) Current consumption (a) S-8253AAA 1. IOPE - VDD
40 35 30 25
2. IOPE - Ta
40 35 30 25
IOPE [A]
20 15 10 5 0 0 5 10 15 20
IOPE [A]
20 15 10 5 0 -40 -25 0 25 50 75 85
VDD [V]
Ta [C]
3. IPDN - VDD
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
4. IPDN - Ta
0
5
10
15
20
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 -40 -25
IPDN [A]
IPDN [A]
0
25
50
75 85
VDD [V]
Ta [C]
(b) S-8253BAA 1. IOPE - VDD
40 35 30 25
2. IOPE - Ta
40 35 30 25
IOPE [A]
20 15 10 5 0 0 5 10 15 20
IOPE [A]
20 15 10 5 0 -40 -25 0 25 50 75 85
VDD [V]
Ta [C]
3. IPDN - VDD
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
4. IPDN - Ta
0
5
10
15
20
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 -40 -25
IPDN [A]
IPDN [A]
0
25
50
75 85
VDD [V]
Ta [C]
Seiko Instruments Inc.
21
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Rev.2.1_00
(2) Overcharge detection/release voltage, overdischarge detection/release voltage, overcurrent detection voltage, and delay times S-8253AAA, S-8253BAA 2. VCL - Ta 1. VCU - Ta
4.375 4.370 4.365 4.360 4.355 4.350 4.345 4.340 4.335 4.330 4.325 -40 -25 4.10 4.09 4.08 4.07 4.06 4.05 4.04 4.03 4.02 4.01 4.00 -40 -25
VCU [V]
VCL [V]
0
25
50
75 85
0
25
50
75 85
Ta [C]
Ta [C]
3. VDU - Ta
2.80 2.78 2.76 2.74 2.72 2.70 2.68 2.66 2.64 2.62 2.60 -40 -25
4. VDL - Ta
2.48 2.46 2.44 2.42 2.40 2.38 2.36 2.34 2.32 -40 -25
VDU [V]
0
25
50
75 85
VDL [V]
0
25
50
75 85
Ta [C]
Ta [C]
5. tCU - Ta
1380
6. tDL - Ta
173 165 155
1320 1220
tCU [ms]
1120 1020 920 -40 -25
tDL [ms]
145 135 125
0
25
50
75 85
115 -40 -25
0
25
50
75 85
Ta [C]
Ta [C]
7. VIOV1 - VDD
0.325 0.320 0.315 0.310 0.305 0.300 0.295 0.290 0.285 0.280 0.275
8. VIOV1 - Ta
7
8
9
10
11
12
13
0.325 0.320 0.315 0.310 0.305 0.300 0.295 0.290 0.285 0.280 0.275 -40 -25
VIOV1 [V]
VIOV1 [V]
0
25
50
75 85
VDD [V]
Ta [C]
22
Seiko Instruments Inc.
Rev.2.1_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
9. VIOV2 - VDD
0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40
10. VIOV2 - Ta
7
8
9
10
11
12
13
0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40 -40 -25
VIOV2 [V]
VIOV2 [V]
0
25
50
75 85
VDD [V]
Ta [C]
11. VIOV3 - VDD
1.5 1.4 1.3
12. VIOV3 - Ta
1.5 1.4 1.3
VIOV3 [V]
1.2 1.1 1.0 0.9 7 8 9 10 11 12 13
VIOV3 [V]
1.2 1.1 1.0 0.9 -40 -25 0 25 50 75 85
VDD [V]
Ta [C]
13. tIOV1 - VDD
10.8 10.4 10.0 9.6 9.2 8.8 8.4 8.0 7.6 7.2
14. tIOV1 - Ta
10.8 10.4 10.0 9.6 9.2 8.8 8.4 8.0 7.6 7.2 -40 -25
tIOV1 [ms]
7
8
9
10
11
12
13
tIOV1 [ms]
0
25
50
75 85
VDD [V]
Ta [C]
15. tIOV2 - VDD
5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6
16. tIOV2 - Ta
5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 -40 -25
tIOV2 [ms]
7
8
9
10
11
12
13
tIOV2 [ms]
0
25
50
75 85
VDD [V]
Ta [C]
Seiko Instruments Inc.
23
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series
Rev.2.1_00
17. tIOV3 - VDD
0.38 0.36 0.34 0.32
18. tIOV3 - Ta
0.38 0.36 0.34 0.32
tIOV3 [ms]
0.30 0.28 0.26 0.24 0.22 7 8 9 10 11 12 13
tIOV3 [ms]
0.30 0.28 0.26 0.24 0.22 -40 -25 0 25 50 75 85
VDD [V]
Ta [C]
(3) COP/DOP pin S-8253AAA, S-8253BAA 1. ICOH - VCOP
0.10 0.08
2. ICOL - VCOP
14 12 10
ICOL [mA]
ICOH [A]
0.06 0.04 0.02 0 0 4 8 12 16 20 24
8 6 4 2 0 0 3.5 7.0 10.5
3. IDOH - VDOP
0 -0.5
VCOP [V]
4. IDOL - VDOP
14 12 10
VCOP [V]
IDOH [mA]
-1.5 -2.0 -2.5 0 1.8 3.6 5.4
IDOL [mA]
-1.0
8 6 4 2 0 0 3.5 7.0 10.5
VDOP [V]
VDOP [V]
24
Seiko Instruments Inc.
3.00 -0.2
8 5
+0.3
1
4
0.170.05
0.20.1 0.65
No. FT008-A-P-SD-1.1
TITLE No. SCALE UNIT
TSSOP8-A-PKG Dimensions FT008-A-P-SD-1.1
mm
Seiko Instruments Inc.
4.00.1 o1.5 -0
+0.1
2.00.05 0.30.05
8.00.1
o1.5 +0.1
-0
4.40.2
6.90.1
1
8
4
5
Feed direction
No. FT008-D-C-SD-1.0
TITLE No. SCALE UNIT
TSSOP8-D-Carrier Tape FT008-D-C-SD-1.0
mm
Seiko Instruments Inc.
60
20.5 Enlarged drawing in the central part o210.8 20.5 o130.2 13.50.5
No. FT008-D-R-SD-1.0
TITLE No. SCALE UNIT mm
TSSOP8-D-Reel FT008-D-R-SD-1.0
QTY. 3,000
Seiko Instruments Inc.
* * * * * *
The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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